BODY HEIGHT | 0.065 INCHES MAXIMUM |
BODY LENGTH | 0.260 INCHES MAXIMUM |
BODY WIDTH | 0.260 INCHES MAXIMUM |
CASE OUTLINE SOURCE AND DESIGNATOR | TO-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND |
FEATURES PROVIDED | HERMETICALLY SEALED AND BURN IN AND SCHOTTKY AND POSITIVE OUTPUTS |
INCLOSURE CONFIGURATION | FLAT PACK |
INCLOSURE MATERIAL | CERAMIC |
INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
TERMINAL SURFACE TREATMENT | SOLDER |
TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
TIME RATING PER CHACTERISTIC | 7.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 6.50 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |