| BODY HEIGHT | 0.120 INCHES MINIMUM AND 0.160 INCHES MAXIMUM |
| BODY LENGTH | 0.745 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-001-AE JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/STORAGE AND PROGRAMMABLE AND PROGRAMMED AND BIPOLAR AND 3-STATE OUTPUT AND W/ENABLE AND W/BUFFERED OUTPUT AND W/DECODED OUTPUT AND W/DISABLE |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 10 INPUT |
| OPERATING TEMP RANGE | +0.0 TO 75.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 625.0 MILLIWATTS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TEST DATA DOCUMENT | 97384-56602-40003 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |