| BODY HEIGHT | 0.100 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 1.200 INCHES MINIMUM AND 1.290 INCHES MAXIMUM |
| BODY WIDTH | 0.515 INCHES MINIMUM AND 0.580 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-015-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 1 ARITHMETIC LOGIC UNIT AND 1 GENERATOR, FUNCTION |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND DARLINGTON-CONNECTED AND W/DISABLE AND W/ENABLE AND POSITIVE OUTPUTS |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 14 INPUT |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 455.0 MILLIWATTS |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 24 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |