| BODY HEIGHT | 0.040 INCHES MINIMUM AND 0.080 INCHES MAXIMUM |
| BODY LENGTH | 0.370 INCHES MINIMUM AND 0.395 INCHES MAXIMUM |
| BODY WIDTH | 0.245 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AG JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 6 INPUT |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 400.0 MILLIWATTS |
| MEMORY CAPACITY | UNKNOWN |
| MEMORY DEVICE TYPE | ROM |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 16 FLAT LEADS |
| TEST DATA DOCUMENT | 35351-151471 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 6.0 VOLTS MAXIMUM POWER SOURCE |