| BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 4 GATE, NAND |
| FEATURES PROVIDED | HERMETICALLY SEALED AND LOW POWER AND MONOLITHIC AND POSITIVE OUTPUTS AND W/TOTEM POLE OUTPUT |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | GLASS AND METAL |
| INPUT CIRCUIT PATTERN | QUAD 2 INPUT |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 4.0 MILLIWATTS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TEST DATA DOCUMENT | 35351-151534 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 60.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |