| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND MEDIUM SPEED AND MEDIUM POWER AND POSITIVE OUTPUTS AND ASYNCHRONOUS AND EDGE TRIGGERED AND W/ENABLE AND W/CLEAR |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 8 INPUT |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | DIODE-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 70.0 MILLIWATTS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TIME RATING PER CHACTERISTIC | 35.00 NANOSECONDS MINIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 30.00 NANOSECONDS MINIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT AND 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |