| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| TEST DATA DOCUMENT | 94117-310403 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 70.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT |
| BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| INCLOSURE MATERIAL | CERAMIC |
| MEMORY DEVICE TYPE | ROM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| INCLOSURE CONFIGURATION | FLAT PACK |
| STORAGE TEMP RANGE | -65.0/+125.0 DEG CELSIUS |
| INPUT CIRCUIT PATTERN | 10 INPUT |
| BODY LENGTH | 0.365 INCHES MINIMUM AND 0.385 INCHES MAXIMUM |
| OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| MEMORY CAPACITY | UNKNOWN |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| TERMINAL TYPE AND QUANTITY | 16 FLAT LEADS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| FEATURES PROVIDED | HERMETICALLY SEALED AND HIGH SPEED AND PROGRAMMABLE AND PROGRAMMED AND W/BUFFERED OUTPUT AND W/DECODED OUTPUT AND W/ENABLE AND 3-STATE OUTPUT |