| DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K/R-S, CLOCKED |
| BODY HEIGHT | 0.050 INCHES MINIMUM AND 0.065 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND W/ENABLE AND POSITIVE OUTPUTS AND EDGE TRIGGERED |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 7 INPUT |
| PRECIOUS MATERIAL | GOLD |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
| PROPRIETARY CHARACTERISTICS | PACS |
| MAXIMUM POWER DISSIPATION RATING | 55.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | DIODE-TRANSISTOR LOGIC |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 8.0 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0 TO 150.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TERMINAL SURFACE TREATMENT | GOLD |
| TIME RATING PER CHACTERISTIC | 40.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT |