| CASE OUTLINE SOURCE AND DESIGNATOR | T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND MEDIUM SPEED AND MEDIUM POWER AND POSITIVE OUTPUTS |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | DUAL 5 INPUT |
| PRECIOUS MATERIAL | GOLD |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
| PROPRIETARY CHARACTERISTICS | PACS |
| MAXIMUM POWER DISSIPATION RATING | 34.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | DIODE-TRANSISTOR LOGIC |
| STORAGE TEMP RANGE | -65.0 TO 150.0 DEG CELSIUS |
| TIME RATING PER CHACTERISTIC | 25.00 NANOSECONDS MINIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 80.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 10.00 NANOSECONDS MINIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT AND 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND-NOR |
| BODY HEIGHT | 0.050 INCHES MINIMUM AND 0.065 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |