BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
BODY LENGTH | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K, AND INPUT MASTER SLAVE AND 1 FLIP-FLOP, J-K, CLOCKED |
FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND EDGE TRIGGERED AND MEDIUM POWER AND MEDIUM SPEED AND PRESETTABLE AND W/CLEAR |
INCLOSURE CONFIGURATION | FLAT PACK |
INCLOSURE MATERIAL | GLASS AND METAL |
INPUT CIRCUIT PATTERN | 9 INPUT |
OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
MAXIMUM POWER DISSIPATION RATING | 110.0 MILLIWATTS |
PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD AND BODY GOLD |
PRECIOUS MATERIAL | GOLD |
SPECIAL FEATURES | MECH-PAKETTE FURNISHED |
STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
TEST DATA DOCUMENT | 02859-5509415 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
TIME RATING PER CHACTERISTIC | 39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |