| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 4 GATE, NAND |
| FEATURES PROVIDED | MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND MEDIUM SPEED AND W/OPEN COLLECTOR |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | PLASTIC |
| INPUT CIRCUIT PATTERN | QUAD 2 INPUT |
| OPERATING TEMP RANGE | +0.0 TO 70.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 160.0 MILLIWATTS |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS SILVER |
| PRECIOUS MATERIAL | SILVER |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TEST DATA DOCUMENT | 20551-A308 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 45.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |