| BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| BODY LENGTH | 0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM |
| BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K/R-S, CLOCKED |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/ENABLE AND AC COUPLED AND ASYNCHRONOUS AND NEGATIVE EDGE TRIGGERED AND RESETTABLE |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 9 INPUT |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 132.0 MILLIWATTS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |