| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0.116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| MAXIMUM POWER DISSIPATION RATING | 38.0 MILLIWATTS |
| OPERATING TEMP RANGE | +0.0/+70.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 34010-50254900 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 5.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 5.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |